1. Field of the Invention
The present invention relates to a semiconductor resistance element used in a semiconductor integrated circuit mainly having a Schottky gate FET (referred to as MESFET hereinafter) or a junction gate FET (referred to as JFET hereinafter).
2. Description of the Related Art
In an integrated circuit device in which a large number of MESFET's or JFET's are formed on a substrate, a resistance element formed on the same substrate is used for connecting between those FET's or to an external circuit in order to, for example, limit a current or divide a voltage. In general, this resistance element is constituted by an impurity region formed on the substrate. That is, the resistance element is formed by patterning an element region on the substrate, then introducing the impurity. The resistance value of the resistance element is determined on the basis of the density of the impurity and the size of the patterning.
This method is sufficient when a highly accurate resistance value is not required in the circuit of the IC device. When, however, a highly accurate resistance value is required, an integrated circuit having a high reliability cannot be obtained.
That is, in the prior art method for forming the resistor on the substrate, the resistance region must be patterned on the substrate, and further, the process of ion implantation, anneal, must be carried out. In these processes, however, due to errors in the patterning size or a varying of the process control conditions, the resistance value of the resistor will vary widely, and accordingly, the resistor formed on the substrate by the prior art method cannot be utilized for a circuit element which needs a high accuracy.